A brief introduction to the core board:
A variety of core board for selection (the core plate data and pictures please view the site of the online store page), the use of FPGA:
(1) Cyclone core: EP1C12Q240C8, EP1C6Q240C8;
(2) CycloneII core: EP2C8Q208C8, EP2C5Q208C8, EP2C20Q240C8; CycloneIII core: EP3C16Q240C8, EP3C25Q240C8;
(5) EPCS1, EPCS16,, EPCS4, EP1C6, EP2C5 and EPCS1, EP1C12, EP2C8 and EP2C20, EPCS4,, EP3C16 (16Mb), EP3C25 (EPCS16);
(6) provide configuration mode: JTAG and AS;
(7) two 50Mhz active clock;
(8) all, Avalon bus and configuration IO pins through leads to 4 rows of pin, users can full freedom to play, expanding more flexible;
(9) 4 LED;
(10) a reset button.
Two, the experimental board V5.0:
(1) 10M Ethernet interface: using RTL8019 chip
(2) 8 bit AD analog to digital converter;
(3) 4 Channel 8 bit DA digital to analog converter;
(4) real time clock;
(5) RS-232 serial port: data communication for the computer;
(6) the VGA interface: direct VGA display and docking, used FPGA to achieve VGA interface protocol to display text and graphics on the display.
(7) PS/2 mouse, keyboard interface.
(8) the 16*2 character type LCD interface can be displayed in English.
(9) 128*64 dot matrix LCD display interface, can Chinese, graphics etc.;
(11) USB interface: USB-UART bridge chip CP2102, compatible with USB2.0 and USB1.1 protocol, the highest rate is 1Mbps, can be directly used for communication rate is not very high, such as industrial equipment, instrument, etc., developers need to understand the USB protocol and design driver, which makes the development cycle is short, the risk is small, the cost is low, and the anti-interference performance is good, the work is stable and reliable, the normal operating temperature range is +85 ~ -40. With the package of the CD, with the chip's data manual, driver, and examples of procedures.
(12) 4 7 digit two segment digital tube.
(13) EEPROM memory based on I2C protocol.
(14) four key switch: uphold the same simple style, not to pursue more, but simple, saving limited IO resources for NiosII external input keys, such as interruption experiment is sufficient